Analog-to-Digital Conversion

Motivation. That binary codes are used to represent symbols (like letters of the alphabet) can seem artificial. That binary codes are also used to represent numbers can seem downright contrived. Why take up eight wires to signal the integers from 0 to 255 when the voltage on one wire might do the job? Just let the wire's voltage vary continuously from say, 0 to 2.55 v!

From the Sampling lecture notes let us bring back the Matlab script, now renamed Test_FFT_11b. Here we convert the perfect 20 samples to N-bit digital numbers which are approximations to the correct values...

Now for the sake of the present chapter, let us take seriously the notion that continuously varying voltages or currents can represent information in useful ways, and that it may be a computer's responsibility to create such analog output. In fact when computers are connected to the "real world" interface circuits are usually required to convert sensor outputs to digital codes and other interface circuits may be required to convert digital codes back to analog voltages needed by actuators. These interface circuits are known as analog-to-digital converters (ADC, for bringing in analog signals) and digital-to-analog converters (DAC, for sending analog signals back out).

Although our goal is to understand conversion, we begin with conversion. DAC's are an internal part of successive approx ADC's.

A basic counting A-D conv. can be made with a DAC, a counter, a pulse generator and an analog comparator. An analog comparator is a 1-bit A-D converter, as you will see later.

Digital to analog converter
A DAC is a linear summation amplifier.
Linearity will be useful in explaining how a summation amplifier works.

Given a function f(x), where x is a real number, what test can you perform to determine if f is linear?
ax1 + bx2) = af(x1) + bf(x2)
for all a, b where x1 + x2 are two different inputs, and a and b are multiplicative constants.
This test for linearity is called superposition; the responses to two separate inputs are "superimposed" for the response to the two inputs simultaneously.

Superposition implies that f(0) = 0. A system can be time-varying, and still be linear.
y(t) = x(t) R(t) is a time-varying linear relationship between y and x.
Linearity, time invariance, and other properties of dynamic systems are discussed in texts such as

Oppenheim & Willsky, Signals & Systems, Prentice-Hall, (1983). See 3.4, "Properties of linear time-invariant systems."

McGillem & Cooper, Continuous & Discrete Signal and System Analysis, Holt-Rinehart & Winston, 1991. See chapter 1.

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Because a DAC is a device with many inputs and one output, it resembles in some ways a nerve cell, which has many inputs on its dendrites and one output on its axon.

The axon, by the way, sends out a pulse-coded signal, to represent the "analog" output. It resembles superficially a serial transmission output.

Mark Bear, Barry Connors & Michael Paradiso, Neuroscience: Exploring the Brain, Williams & Wilkins (1996)
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General form of a DAC

Recall how to convert from base 2 to base 10 numbers.
Let a 4-bit base-2 number N = B3 B2 B1 B0, where we expect N to be a non-negative integer. The base-10 version N10 is

Each digit in the base 2 number is multiplied by a factor which is a power of 2 greater than the factor which multiplies its less significant neighbor. Digital to analog conversion will follow this method, by weighting the bits in a binary number with power-of-2 increasing influence, as the bits form inputs to a summation amplifier.

A DAC can have anywhere from 2 to 16 digital inputs, and one analog output.
The inputs will represent a number, not a symbol.
Shown below is the general form of a 5-bit DAC:

What do we want from a digital-to-analog converter? We could want something as literal as an output voltage equal to the number value of the binary code presented as input. Such a specification could result in the following input-output graph for a 3-bit D2A converter:

And if we sent the output of a 3-bit counter to a DAC, we would see such a staircase waveform on a oscilloscope, in time with the counter's clock. [We'll see later that an offset of the curve shown above provides an output with reduced error.]

Summation amplifier
You've seen some of this development in the earlier chapter on amplifiers: Imagine an analog circuit which maintains its input at "virtual ground"-a voltage almost equal to zero. By Ohm's Law, a feedback resistor RF from VOUT to virtual ground carries current VOUT/RF.

Now connect a "source voltage" VS to the virtual ground through a resistor RS,

The circuit continues to maintain virtual ground at nearly zero volts. The current flowing from VS to virtual ground is VS/RS, in the direction shown by the arrow. Kirchoff's Current Law (KCL) says that the current flowing into a circuit node must equal the current flowing out. One of the means by which an op amp maintains virtual ground: it allows virtually no current to flow into itself from the virtual ground node, due to a "high input impedance."

With currents Is and If both shown flowing into the virtual ground, and no current flowing into the op amp, KCL requires
IS + IF = 0. Say we declare that current flowing into a node is positive. Then if we substitute our Ohm's Law voltage expressions into the current equation we find

The ratio RF/RS is the gain of the circuit. A circuit with large differential gain and large input impedance can maintain a virtual ground is called an operational amplifier, or op amp. By adjusting resistors RF and RS we can achieve various negative gains from source input VS to VOUT. Don't confuse the source voltage VS with the amplifier input! The amplifier input is held to virtual ground! A voltmeter on the virtual ground will show a reading almost equal to 0.0. If VS is restricted to digital values, we have created, with our op amp, a 1-bit digital-to-analog converter.

If input comes directly to virtual ground from a current source IS, then VOUT = -IS RF, and we will have a current-to-voltage converter.

By hooking two op amps in series, we can obtain a positive-gain amplifier:

If all the R's are the same value, the gain will be +1.0, and VOUT = VS.
Notice that the op amp on the left must be capable of supplying

amount of current, because VOUT1 is the input to the second op amp.

Mention high gain...for below

If you're curious about how an operational amplifier maintains virtual ground at nearly zero, read the discussion after the DAC lab in JD's Lab Manual +.
Actually an op amp has two inputs, V+ and V-, and an op amp with no feedback resistor (think of Rf as an infinite resistance) multiplies the difference between V+ and V- by a huge number, like 10^5 or 10^6. The input we utilize in our negative gain circuit is V-, while V+ is grounded.
Virtual ground is maintained by a negative feedback mechanism. RF is the feedback resistor, going back to the negative input. If the differential gain is large, then only a small voltage difference between V- and ground is needed to keep VOUT at a level which will balance current flow into the virtual ground.

As we noted previously, the resistance between the minus and plus inputs is also huge-10^12 W or so at low frequency-the huge input impedance enforces the negative gain formula -RF/RS by preventing current from flowing into the V- terminal.
Op amps are versatile analog building blocks, useful for filtering, waveform generation, etc. If you'd like to know more about how op amps work, see my Lab Manual, which explains various other of op amp configurations for positive gain, unity gain, true differential gain, perfect diode, etc. Other references are-

James K. Roberge, Operational Amplifiers: Theory and Practice, John Wiley & Sons, 1975. 
See chapter 1. 

Graeme, Tobey & Huelsman, Operational Amplifiers, Design and Applications. McGraw-Hill, 1971. See chapter 6, "Linear circuit applications."

(1) Horowitz & Hill, The Art of Electronics, 2nd Edition, (Cambridge University Press, (1989)

Output saturation. Suppose, for an op amp, (input x gain) is a large number, like 100. Will the op amp deliver 100 volts at its output? No, generally an op amp is limited in output range to +/- 12 to 15 volts. An op amp, in fact, requires a +/- 12 to 15 volts dual-output power supply, as well as ground. If the op amp output is at the maximum (+12 volts) or the minimum (-12 volts) it is said to be saturated. An op amp in saturation is no longer a linear amplifier.
A DAC should be designed to avoid the saturation limits of an op amp by limiting the output when all logical inputs are 1. To prevent saturation, make sure that when only the MSB input is HI that the op amp output is less than half the saturation voltage.

A 2-bit DAC
An op amp output responds to input current, as dictated by VS and RS and their associated resistors-it's a current-to-voltage converter. What if a second source voltage, VS2, is applied to virtual ground through a second resistor, RS2, supplying a second current to the virtual ground input node?

The current supplied by VS2 results in another term for Kirchoff's Current Law, and now (because of linearity) VOUT becomes,

The feedback resistor RF is common to both terms, so can be factored out.
VOUT when VS1 is applied alone, and VOUT when VS2 is applied alone, are added together to give the VOUT which results from the simultaneous application of VS1 and VS2. The plus sign in the formula is the algebraic kind of plus-addition-not logical OR!

The 2-source-input circuit can become a 2-bit digital-to-analog converter if we make one source resistor twice as big as the other, and restrict the inputs VS1 and VS2 to digital values. To be specific, let

RS1 = 1KΩ
RS2 = 2KΩ
RF = 1KΩ,
and LO = 0 volts
and HI = 3 volts
then the following "truth-table" results

It's not a genuine truth table because the output is listed as voltage instead of logical 0 or 1.

Our assumption that logical 0 is represented by 0.0 volts may be unrealistic.
In the TTL logic family LO outputs are typically  0.2 volts = VCEsat, and TTL inputs don't care if logical 0 goes as high as 0.7 volts!
If logical 0 is 0.2 volts, and RF = 5K, then for a logical input of "00" our 2-bit DAC will have an output of

, which is a lot different from zero millivolts-what we had been hoping for. The 120 mV is an offset error. One fix: use CMOS gates to drive the DAC resistors. CMOS chips generally stay close to 0 volts for LO output, and close to +5 volts for HI output. Depending on the quality of a chip output may be a risky way to insure a linear DAC response. Below is described a better way to combat offset error.

Analog switches and a 3-bit DAC
To insure that the summation amplifier sees zero volts as VS when the logical input is LO, we call upon SPDT single pole double throw switch.

The control for this switch is the logical input intended for the DAC. The control makes the switch choose between zero volts (ground) and "something else," which we call VREF. VREF does not need to be greater than VIH, because it's role is to provide a non-zero VS, driving current toward the virtual ground. Since the switch's two inputs don't have to be within the ranges for any logical LO or HI convention, this device is called an analog switch. Analog switches in practice are made from MOS transistors. The analog switch is a buffer between the logic level inputs and voltages needed by the DAC for linear behavior.

Even logical HI varies from one logic family to another, and it can be affected by load conditions. VREF will provide peace of mind that logic HI is producing consistent behavior on all the DAC inputs. VREF itself can be any reasonable voltage, even negative.

Analog switches in the service of a 3-bit D-A converter would look like,

where the most significant bit (MSB) sees the lowest resistance between it and virtual ground, and the resistors are arranged in power-of-two size differences. We are assuming our analog switches are "perfect," and offer no resistance or offset voltage.

You can see a 4X single throw analog switch set in the lab: the 4066 chip drawer.

Multiplying DAC
Imagine the 3-bit analog switch network above connected to an op amp with
RF = 1K-Ohm. Let VREF be 3.0 volts. What is VOUT when the input code = 111?
The system is still linear, so we can add up the influence of the three individual inputs. VREF can be factored out with RF.

If VREF is made a variable, then we have built a multiplying DAC! The circuit multiplies VREF, an analog variable, times the digital input. Yes, RF could also be a multiplying factor, but resistance is much more awkward to vary electronically than voltage, so a multiplying DAC always multiplies an analog reference times a digital code.

So far the multiplying DAC is a two-quadrant multiplier; VREF can be a positive or negative voltage, and the digital input is a natural positive integer.

Negative and positive DAC outputs: Negative numbers can be expressed in in 2's complement code:

with a 3-bit realization shown below:

If you want a non-multiplying DAC, just tie VREF to some convenient voltage like +5v.
The 7524 (Analog Devices) is a low-cost 8-bit multiplying DAC which uses CMOS analog switches to flip between VREF and a ground rail; the 7524 requires an op amp at its output to convert current to voltage; it has a latch on the 8-bit input. We'll use the 7524 as an example when we discuss accuracy and timing spec's of ADCs.

If our DAC design were extended out to 8-bits,
we would need eight resistors, in the ratios

1 2 4 8 16 32 64 128

which is quite a range of resistors to keep on hand. For manufacturers of integrated circuit ADCs a range of 128 in resistor values is impossible to fabricate on a single chip. A solution is found in the R-2R ladder that uses twice as many resistors, but requires only two values. The 7524 has an R-2R ladder using 10K-ohm and 20K-ohm resistors. More information on the R-2R ladder in a problem at the end of the , and in the 7524 data sheet.

Another aspect about DAC resistors: It really matters whether a resistor is 2K, 1.9K or 2.1K. Real resistors can vary from their marked values, by up to 10%. The quality of a DAC may depend on precision with which resistors match each other. Analog integrated circuit manufacturers sometimes use laser "trimming" to bring IC-fabricated resistors into specification.

Digital-to-analog converter specifications
Specification begins with the analog output: What are the maximum and minimum voltages to be reached, and with what resolution? If the minimum voltage needed is not zero, then some offset must be built in, by a resistor connected between virtual ground and a fixed voltage. Shown below is a 4-bit R-2R ladder DAC, with an offset of -1.25 volts. When input = 0000, output = -1.25 volts.

Not shown are the analog switches and VREF on the 4 inputs.
The maximum output can be set by adjusting VREF and/or RF when logical input = 1111.
In the circuit above,

Resolution is the smallest voltage difference to be expressed at the analog output. If you know VMAX, VMIN, and the resolution required, you can compute the number of bits needed. Subtract VMIN from VMAX and divide by the resolution to find the minimum number of steps. Then find the next largest power of 2 greater than the number of steps, and you have the number of digital bits N required (resolution) to span the output range.

Examples: An analog output may go as low as 0 volts and as high a +5 volts. The output should change by less than 0.1v for a one-step digital change. How many digital bits are required?

An 8-bit D-A converter spans a range of +5.12 volts to -5.12 volts. What's the resolution?

The 7524 has a resolution of 8 bits; it can produce 28=256 different analog outputs.

Accuracy is a measure of what voltage is expected at the output vs what actually appears. For example, if a 4-bit DAC with an assumed gain of 1.0 and an input code of 1010 is expected to generate 10.00 volts, but actually delivers only 9.80 volts, the accuracy of code 1010 would be

. If its performance at code 1010 were its worst, then the accuracy of the DAC itself would be 2%, otherwise whatever usable code with the worst accuracy would govern the rating for the DAC. Accuracy can be compromised by lack of precision in matching of resistor ratios, by a reference voltage improperly set, or by a non-linear gain function in the op amp. For example, if the resistor on the LSB is too small, then the LSB will have undue influence on the output, and, in the worst cases, can cause non-monotonic behavior, whereby a binary code for N produces a lower analog output than for a smaller number N-1. Non-monotonic behavior, as we will see, can produce missing codes in analog-to-digital converters.

Settling time. Consider a 4-bit DAC that must change from 7 to 8, due to input change of 0111 to 1000. All the input bits are switching at once. If the analog switches in the DAC bits change slower from LO to HI than HI to LO, then there will be a brief instant when the DAC output drops to 0 before jumping up to 8.

The output is not valid until the glitch is over. The glitch might be filtered out, but the filter would reduce the speed of switching (bandwidth) of the output. The time, including propagation delay through the switches, it takes the DAC to come within 90% of a new value is its settling time. The 7524 has a 150 nsec settling time; which does not include the dynamics of the op amp to convert current to voltage.

DACs in raster scan graphics displays-p. 152 ff in AD book.
Need for high speed 15 nsec settling time. 7524 would not be fast enough.

Assume sampling theorem has been mentioned... must sample at rate greater than twice highest freq of input or higher frequencies will be aliased as lower frequencies. May need sample and hold circuit to capture waveform for duration of A-D conversion.
Having worked to understand digital-to-analog converters,
let's use one right now in a recipe to make a 4-bit analog-to-digital converter (ADC).
We'll also need to involve an analog comparator. An analog comparator,
such as the LM311, has a binary output of HI if its V+ input > V- input, and a LO output if V+ input < V- input.
The two inputs V+ and V- do not need to be binary: they can be any analog value, in principle.

Counting converter for analog to digital
*Connect an up-counter's outputs to a DAC's digital inputs,
making sure to hook up the counter's MSB to the DAC's MSB, and so on.
*Connect output of the DAC to the V+ side of an analog comparator like the LM311.
*Connect the unknown Analog input = AIN to the V- side of the comparator.
*Start by CLEARing the counter to 0000. Send pulses into its clock.
*With each count up the DAC output will increase by a step.
At some point it will become greater than analog-in, and send the output of the comparator to LO.
*When the comparator output switches from 1 to 0, have it disable the counter;
*The output of the counter at the time it's disabled is the answer!
The answer is a 4-bit digital code which represents analog-in.

Let's back up and look at what we've got.

1. The "answer" will be the same digital code for a sub-range of AIN values equal to the voltage resolution of the DAC. For example, if the DAC changes by volt every step, then there will be an uncertainty of about volt as to what the "true" AIN is.

2. Unlike DAC output, the counting ADC output is not determined "instantly." Because of the presence of the counter, this ADC is a "sequential" circuit. In fact, the 4-bit counter may have to step through 2^4 clock pulses to find the right answer. We may have to arrange that AIN does not change during the time interval in which the conversion takes place.

3. The counting ADC signals the End of Conversion (EOC) process by sending the comparator output LO. We must make sure the maximum output of the DAC > the maximum possible AIN. An external circuit reading the counter output can use the EOC signal to know when to store the correct answer in a register.

4. Our counting ADC needs a Start of Conversion (SOC) signal to get going; in this case SOC clears the counter, and the DAC output falls immediately to 0. [As long as AIN is a positive voltage, the comparator output will go HI when the counter is cleared.] To make the ADC operate on "free-running" basis maybe we could connect EOC to SOC. Will a direct connection work, or will we need a 1-shot on EOC?

5. The analog-in and DAC-out ranges should match. Analog-in presumably can be any voltage AIN such that
If the DAC output maximum is greater than AIN-MAX and DAC minimum is less than AIN-MIN, then the system is guaranteed to resolve any AIN value within ± LSB worth of voltage, where "LSB worth of voltage" is the step size on the DAC staircase. As shown below, some of the states of the counter may be unused if the DAC range is much greater than the AIN range.

For maximum resolution, we'd like to utilize all 16 states of the counter. One way to do that would be to lower the gain of the DAC until it spans only a sub-range of AIN's possible values. However, that might mean that many large values of AIN would all convert to 1111, or that many low values of AIN would convert to 0000.

To accomplish a full-resolution match-up, the maximum DAC output (from 1111 counter input) must be slightly greater than AIN-MAX, and the minimum DAC output (0000 on counter) must be within a LSB of AIN-MIN. See below.

If AIN exceeds the maximum value of the DAC output then the comparator will never trip, even for 1111, and an EOC signal will never be produced. In fact, the counter will rollover to 0000 if AIN is too large! Perhaps the ADC needs an "overflow" flag, which comes on when the counter rolls over.

Analog comparator revisited
In S4, example 2, we introduced the analog comparator, which responded with logical HI or LO output depending on whether one of two analog inputs was greater or less than the other. The analog comparator is a 1-bit A-D converter.

In terms of op amps, think of the comparator as a summation amplifier with high gain, and output limits (saturation) of +5 volts and 0 volts. [Threshold would present itself as negative q volts, versus AIN's positive voltage.]

A well-known analog comparator is the LM311, with open-collector output. If the inputs of a 311 are nearly equal, then the output can "chatter" (pulse up and down). Chatter can occur even if AIN is just crossing the threshold, going from a low to a high value, or vice versa.

By sending a fraction of the comparator output back to the + input we can build in a little positive feedback hysteresis and eliminate the chatter.

Here we show the hysteresis resistor RH and the AIN source impedance RS.
Assume RH >> RS, say 100KΩ vs 100Ω.
If DOUT = 0, then no voltage is fed back to the S point, and the 311 will wait until AIN > q before snapping HI.
If DOUT = 5 v, then the voltage at S is

This formula assumes that the analog comparator, like the op amp, has relatively high input impedance, and little current enters terminal "V+" . Also, AIN and the comparator output voltage should be referenced to the same ground. The hysteresis effect works because of saturation in the comparator output. When DOUT snaps to HI it provides a steady+5 volts for the feedback circuit. The positive feedback can't "run away" because DOUT is at its maximum value. The hysteresis curve is shown below, with arrows indicating the direction of change of AIN. Once DOUT goes HI after AIN crosses q, it won't go LO until AIN drops below

. A system with hysteresis has a kind of memory for the input's recent history.

To the right is a timing diagram illustrating the effect of adding hysteresis to the analog comparator. Both with and without hysteresis a rising, noisy AIN will cause a switch at q.
Curing chatter in the comparator looks a little like de-bouncing a switch. Along that line of thought, two analog comparators, connected to the SET and RESET of a flip flop can be used to "de-chatter" an analog transition across a threshold q.

The width of the hysteresis region of the above circuit is thetH - thetL. No resistors are needed on the comparators.
By requiring θH > θL we insure that SR=11 will never occur.

A 555 timer chip has a front end like the circuit above, with two comparators and a flip flop. [What would happen if OUT were connected through an inverter to AIN? With the addition of a switch and an RC network, that's how the 555 becomes an oscillator.]

Fla$h converter, analog-to-digital
The 1-bit ADC made with a comparator needs no clock and responds "instantly" to changing analog input. We can use more comparators to improve resolution of our "flash" ADC. First establish three thresholds, using the chain of equal resistors on the right of the drawing below. Let these thresholds go to the V- inputs of three analog comparators.
Send AIN to the V+ inputs of all three comparators.

Now verify that only four conditions of comparator outputs ZYX are possible,
as listed below








Ain < 1/4




1/4 < Ain < 1/2




1/2 < Ain < 3/4




3/4 < Ain

The table gives us digital codes for 4 regions of AIN, meaning 2-bit resolution. It's a matter of Boolean reduction to trim our 3-bit representation to a more conventional 2-bit form (BA, below), which can go directly into a 7-segment display driver.

0 0 0 0 0
0 0 1 0 1
0 1 1 1 0
1 1 1 1 1

What should B be? Y! What about A? X xor Y xor Z will work, as will Z and X xnor Y

To make an N-bit flash conversion we need 2^N - 1 comparators. For an 8-bit conversion 255 comparators are required! A costly proposition, but necessary where blinding speed is required (in radar, for example). (Try the AD9002-B 8-bit flash converter, with 160 MHz bandwidth, 750 mW power consumption and a cost of $200 per chip, or the 6-bit, 200 MHz, AD9006, at $320 per chip, for use in digital oscilloscopes.)

Error in ADCs

The 4-bit flash converter gives us an opportunity to look at the size of error in ADC's. Consider the situation where AIN is just barely smaller than 1/4 VREF. The converter gives digital 00 as an output.

We can say "error = LSB," since the LSB output changes at AIN = 1/4. What happens to error if the bottom resistor is R? The size of the 0 error is reduced to 1/8 = 1/2 LSB.
Add another R to the top of the chain, to maintain a total resistance of 4R.

If our desired answer goes through the middle of the staircase of analog choices then error will be minimized. (except near AIN-Max.)

The error will be ± 1/2 LSB for most of the range.
This graph isn't of concern to DAC design...there we just want 000 = 0 v, 001 = 1 v, etc, as usual.

Sub-ranging flash converter

If we're willing to put up with a little more propagation delay, we can reduce the number of comparators in an 8-bit flash converter from 255 to 30. Here's how, with a sub-ranging flash converter. [Sub-ranging has intimations of the successive approximation method.]

The top flash converter, for the 4 MSB's, should not have an upper R/2 in its resistor chain, so the output of the DAC is always lower than actual analog input. See DAC diagram at the lower right, above. By making sure the DAC output is always less than AIN, the subtraction at the op amp results in a positive (or zero) voltage for the lower flash converter.

How to set the reference for the lower flash converter? The subtraction will result in a positive value always less than or equal to the LSB of the upper flash, so set the reference of the lower flash to the LSB of the upper flash.

A 4-bit flash converter uses 24-1 = 15 comparators, so the subranging 8-bit converter uses 2 x (24 - 1) = 30, instead of 2N-1 = 255 comparators. There is some small cost in speed, because the LSB's take longer to settle, having to pass through a DAC, an op amp, and another 4-bit flash converter before the answer is ready.

Example: Suppose there is a maximum 10.24 volt range on the top flash converter.
Apply an AIN that results in a 1010 0011 = A316 answer. What is your best guess as to the original value of the AIN that caused the A3 answer?
10240 mv / 256 = 40 mv per bit = LSB size of bottom converter.
10240 mv / 16 = 640 mv per bit for the top converter.
Converting to base 10, A16 = 10.
10 x 640 mv = 6.4 volts, (or 10 x 16 = 160. 160 x 40 = 6400 mv = 6.400 volts.)
For the bottom converter, 3 x 40 = 120 mv.
6400 + 120 = 6520 mv = 6.52 volts = AIN, best guess.

In other words, The top flash ADC gives a 1010 answer, which will be converted back to 6.4 volts by the 4-bit DAC, then subtracted from 6.52 volts, giving 0.120 volts.
0.120 volts applied to the bottom DAC.
(which must have a maximum range of 10.24/16 = 640 mv)
results in a 0011 for the 4 LSB's.

Derenzo, Microcomputer Interfacing, Prentice-Hall, (1990) has a good discussion of sub-ranging A/D converters on page 114.

The flash converter needs no clock-timing. Sub-ranging is a version of successive approximation; it first finds the "neighborhood" of the correct answer, then "searches" in that neighborhood for the complete answer.

Successive approximation A-D converter

(Back to lower-cost ADC's, which use a clock.) Now let's look at a conversion technique that is faster than counting, and has the same time per conversion no matter what the magnitude of AIN -- successive approximation.

Recall the counting converter; its search technique for finding the digital answer is unimaginative. For a 9-bit conversion, It's like looking up the definition of "oxymoron" in a 512 page dictionary by starting on page 1 and flipping through page after page until you come to the page with ox's. Better to make a guess as to where oxymoron might be, open the dictionary and see what words are on that page. Depending on whether you've turned to a page before or after the ox's, try another page by going forward or backward accordingly. Each time you turn to a new page, compare the words on it with the word you want, until the search ends with a match.
Using the dictionary analogy, we've just described in words the successive approximation search method.

The successive approximation method applied to A-D conversion replaces the N-bit counter with N SR unclocked latches. Like the counter outputs, each latch output goes to a DAC input. As shown below, the S and R inputs are driven by combinational logic, as we've seen in sequential circuit design. One input to the combinational logic comes from the comparator, while the other inputs come from a 1-hot sequencer.

The 1-hot sequencer is shift-register driven by a clock; on each clock pulse one HI bit is cycled from one output to the next. Only one output is high at a time.

A timing diagram is shown in the next figure after the SA circuit diagram.

The successive approximation process begins with a guess in the middle of the range--for 4-bits the first guess is always
Q3 Q2 Q1 Q0 = 1 0 0 0.
If the guess results in a DACOUT > AIN then Q3 is RESET to LO and the next guess, 0 1 0 0 is tried.

Here are the waveforms expected from the sequencer for a 4-bit SA converter, and the action taken at each point in the successive approximation cycle. The sequencer should contain a serial-in, parallel-out shift register. A combinational gate will determine what serial in should be as a function of the parallel outputs. (See end-of-chpt exercise.)

Could the RESET of bit N and the SET of bit N-1 take place on the same clock pulse?
The HI pulse out of the last sequencer pin can be the EOC signal; SOC can enable the sequencer.

Successive approximation always takes the same number of clock cycles. For the timing example shown 2N clock cycles for an N-bit conversion. Compare the SA conversion rate to the counting converter, which will take much longer, on average 2N-1 clock cycles.

For both conversions we assume the unknown analog input is held at a constant value during the conversion process, an assumption we will discuss at the end of this chapter.

A "163" example lab linked here will show you the gates in "Combinatorial Logic for S-R Inputs" in the Succ. Approx. block diagram above.

A software example
A successive approximation A-D converter can be built entirely with hardware, digital and analog, or the analog part can be satellite hardware for a computer which executes the successive approximation "search" algorithm. As a lab or homework exercise you can fill in the design of an all-hardware SA converter. With a computer, it's also possible for the SA algorithm to de done in software, as we shown in the next figure. The computer shown is capable of sending and receiving bits, via interface "ports," from a DAC and a comparator. It runs a SA program, written here in pseudo-code.

Our pseudo-code initializes for N-bit resolution.
As part of its routine, the computer can receive and send SOC and EOC signals.

The software SA converter will finish conversions only as quickly as the code executes, which in most cases would be an order of magnitude or more slower than a hardware SA converter.

Notice also that the SA converter does not have the hang-up of the counting converter: when presented with Ain greater than the largest output of the internal DAC, the counting converter will not emit an EOC signal. SA converter will converge on 1 1 1 1 ... as an answer for any Ain greater than the greatest DAC output.

Tracking converter
The counting converter and the SA converter needed to start over with every conversion. Can we design a converter which works faster by using the previous answer to help determine the next one? If the next AIN hasn't changed much, the tracking converter can start with the previous value as a guess.

Let's utilize an up/down counting capability-if AIN is increasing, count up, if it's getting smaller, count down. The counter never needs to be reset. See figure below:

The tracking converter acts like a servo. Unless AIN is changing rapidly, the tracking converter will be near the correct answer. The digital answer will be continually be jumping between two values, one bit greater or one bit less than the (unattainable) correct answer.

The counter must stop if it reaches 0000 or 1111, and issue an "overflow" signal to alert the user that AIN may be larger or smaller than allowed. If the count direction is locked at up or down, then the tracking converter becomes a peak detector, only changing when AIN becomes larger or smaller than the previous maximum or minimum. If we add a "synchronizing" feature, we turn the tracking converter into a D-modulator.

Voltage-to-frequency converter
Suppose we have a circuit which behaves like a nerve cell axon--it converts voltage input to pulse frequency output. Such a chip is a voltage-controlled oscillator(VCO), and is the 4th special-purpose interface chip we have encountered (the others--analog comparator, 1-shot, op amp). Perhaps it will be easier to think about how a VCO works if its called a "current-controlled oscillator." Without going into detail consider a current source input charging an RC network

The greater the current, the faster the charging of C. When Vcap exceeds qH Q is SET and closes the switch, discharging the capacitor through RD. When Vcap drops to less than qH then Q is RESET and the capacitor charges up through RC, again proportional to the current input.

[The 654 (Analog Devices) is a VCO with a nearly linear relationship between voltage applied and pulse frequency out. The 654 is an 8-pin, open-collector output chip whose frequency range is determined, like a 1-shot, by a resistor and capacitor attached to the chip.]

The idea behind voltage-to-frequency AD converter: Let AIN drive a VCO; the pulses from the VCO are counted for a calibrated time interval. See circuit below.

To begin a conversion, the calibrated timer directs the counter to clear on its falling edge. During the calibrated interval the counter is enabled for VCO pulses. At the end of the count interval the falling edge latches the counter value, which represents the ADC answer. The second 1-shot clears the counter with a brief pulse and can also start the first 1-shot, if we want a free-running ADC. By adjusting the rate at which pulses come out of the VCO we might be able to get the display to show volts, without need for any other decoding.

We need to make sure the counter won't overflow for the maximum Ain we expect over the counting interval. Over the calibration interval, the V to!freq converter is an integrating converter: it averages the AIN over the time of conversion, unlike the previous ADC's we saw, which provide an answer to AIN at a certain point in time.
Since it integrates, The V to!freq converter doesn't need a sample-and-hold circuit.

Dual-slope converter:
Another integrating ADC is the dual slope. It's found in digital multimeters (DMMs).

To understand the dual slope ADC, you must understand what happens when the feedback resistor RF on a summation amplifier is replaced by a capacitor, C. The current IC through a capacitor is proportional to the rate of change of voltage across the capacitor:

See diagram and equations below.

The current through Rs and the current through the capacitor C are summed to zero, and the resulting linear first order differential equation is solved for an integral relationship.
The output is the negative integral of the input waveform.

In the dual slope design we employ an analog switch on the input of an integrating op amp. The switch acts as a 2 to 1 MUX.

One of the MUX SELECT choices is AIN, a variable positive voltage, the other choice is -VREF, a fixed negative voltage. A control circuit/timer determines when the switch changes.

The output of the integrator goes to one side of a comparator, the other side of which is grounded. The comparator detects when the integrator output crosses zero.

As with the V-f converter, there must be a timer-controller which allows AIN to be the integrator input for a calibrated amount of time (say 250 msec in some DMM's).

After the interval when AIN has access to the integrator elapses, the integrator is presented with -VREF, by action of the analog switch. Since -VREF is the opposite polarity of AIN, the integrator output will reverse its direction, heading back for zero volts (where the comparator is waiting to detect its crossing). Effectively, the VREF action discharges the capacitor.

During the time the integrator is going back toward zero, a counter is enabled to count up at a steady rate. When zero is crossed at the comparator, the counter is stopped and its output latched, for display or memory. At the end of a dual slope cycle, the integrator has reset to zero. The comparator provides an EOC signal and can direct the timing circuit to re-switch the integrator input back to AIN, starting the cycle over again (before -VREF has time to upset the integrator!)

The waveform below shows what the +integrator output looks like during a typical conversion cycle:

We haven't yet said much about what happens to an ADC output if the analog input changes during a conversion (mostly because it's not good!), however, the dual slope and the voltage-to-frequency converters handle changing AIN(t) by integrating over an interval, thereby averaging AIN(t) and finessing the problem of rapidly changing AIN(t).

limitation--all analog inputs have been positive for a negative ref. What to do if the analog input results in a negative integration?

Specifications and extra features of A/D converters

The major specifications concerning A-D conversion deal with time, and with amplitude of the analog input.

Amplitude quantization
The A-D conversion process produces an inherent uncertainty what the true analog value was which generated a given digital code. Consider various parameters of the process. First, the AD converter will have an AIN-min and AIN-max below or above which the input amplifier will either saturate or malfunction. AIN-max - AIN-min is the full scale range (FSR). The FSR can be divided into sub-ranges, called code widths, over which a unique digital word will be the output. Normally the number of steps on an analog-digital graph, and the number of unique digital words, is equal to 2N, where N is the resolution in bits of the converter. However, input ranges which never access code 0000, or code 1111, or nonlinearities which create missing codes, call reduce the number of available codes to a number less than 2N.

While a number of different codes can be used in the digital words, let us, in this discussion, work with the natural binary sequence. Then AIN-min is converted to 0000 etc and AIN-max is converted to 1111 etc. If the actual voltages applied to the ADC are in a sub-range of {AIN-min, AIN-max}, then some of the lowest and highest codes, like 0000 and 1111 may never appear at the digital output.
The midpoint of each code width can be considered from an actual and a calculated point of view. From a calculated point of view we have

Example If AIN-max = 10.24 volts, AIN-min = 5.12 volts, and N = 6, then d = 80 mv.

For M = 27, the calculated midpoint voltage = 2.12 volts.

When the calculated (hoped for) midpoint voltages are compared with the measured midpoint voltages of the code widths (code ranges) a measure of accuracy results. Absolute accuracy is the difference between the calculated and measured midpoints, for each code.

To continue the example from above, if for M = 2710 = 011011 the actual midpoint voltage is 2.00 volts, then the absolute accuracy is 0.12 volts.

If the percentage deviation of the actual from the predicted analog voltage for the full-scale output is computed, then relative accuracy is the result. The diagram below shows some of the amplitude-related specifications of the preceding discussion. The relationship between analog input and digital output starts out at ideal, then wide code widths, narrow code widths, and missing codes are shown, due to non-linearities in the ADC.

Non-monotonic behavior in the ADC will result in missing codes from the output.

Timing specifications
The flash AD converter is in a category by itself, with no clock, and only settling, or propagation delay, between analog input and digital output. For example, the AD9002 8-bit flash converter has a propagation delay of 3.7 ns.

The successive approximation is much faster than the counting converter; an 8-bit conversion can be done in about 8-20 clock pulses with SA. With a 2MHz clock, the 7576 chip can finish a conversion in 10 msec. To perform at maximum rate, the SOC signal may be generated from the last pulse of the 1-hot sequencer used to test each of the bits (send EOC back to SOC).

Integrating converters like V to!f or dual slope have internal pulse generators and counters and are not usually used in speed sensitive applications.

There are environmental specifications, too: Effective temperature range, power supply tolerance, reference voltage sensitivity.

Specs of the old 7576 AD chip

As an example consider the specifications for the 8-bit 7576 successive approximation converter. It's an 18 pin chip that costs about $7.

+ various ABSOLUTE MAXIMUM RATINGS for analog input, VREF, etc.

Analog-Digital Conversion Handbook, 3rd Edition, by the Engineering Staff of Analog Devices, edited by D. Sheingold, Prentice-Hall, Englewood Cliffs, NJ, 1986. Chapter 11, "Specifying converters."

In addition to timing speed and amplitude quantization, A-D converter chips can have features which enhance and streamline their connection to data acquisition systems.
First of all,
SOC and EOC allow external control and monitoring.
Other features can include
On-board register to hold last valid answer (reg clocked by EOC)
Enable control for 3-state output; the digital output can be attached to a bus.
Separate analog and digital "ground" pins.
On-chip clock
On-chip reference voltage
On-chip sample-and-hold circuit (see paragraph below)
Analog multiplexer on AIN for converting signals from various sensors.

Sample & Hold

Up to now we've avoided the issue of what happens if AIN(t) changes during the A-D conversion process. For example, what if, several counts before the counting converter reaches the right value for its DAC to trip the comparator at a particular (large) AIN, AIN suddenly drops to a much lower value. The conversion process will stop, because the comparator trips, but it will stop at a counter setting less than the original large value, and more than the new low value of AIN. It makes two errors at once!

Two of the A-D converter types--voltage-to-frequency and dual slope--avoid the problem of rapidly changing AIN(t) by integrating and averaging AIN(t) during the conversion process.

Another ADC--the flash--can convert at rates up to 200 MHz and will seldom encounter dAIN(t)/dt's which cause error.
But for an ADC such as successive approximation, which needs several clock cycles to complete a conversion, it may be necessary to have a special circuit which holds the value of AIN(t) at the time SOC occurs, and sample for a new value of AIN(t) at EOC.

With a sample-and-hold circuit on the front end of the ADC, at least the correct answer to the held value will be found. But there is a theorem, the sampling theorem, which we mention without proof, that says the ADC must sample at a frequency at least twice as high as the highest frequency in AIN(t), or aliased waveforms--high frequencies disguised as low frequencies--will appear at the ADC output. For example, a 500 Hz sine wave must be sampled at least 1000 times per second to avoid aliasing.

Before the sample-and-hold circuit then, may be needed an anti-alias filter to eliminate high frequency components of AIN(t). GRAPHIC needed...

Herbert Taub & D. Schilling, Digital Integrated Electronics, McGraw-Hill (1977) Chapters 13, "Analog switches" and 14, "Analog-to-digital conversion," are worthy introductions to these two topics. And see reference from Analog Devices, of Norwood MA.