sign_schematic Project Status (12/07/2011 - 23:28:35)
Project File: LabCPost.xise Parser Errors: No Errors
Module Name: sign_schematic Implementation State: Placed and Routed
Target Device: xc3s500e-5fg320
  • Errors:
No Errors
Product Version:ISE 13.2
  • Warnings:
114 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 47 9,312 1%  
Number of 4 input LUTs 38 9,312 1%  
Number of occupied Slices 42 4,656 1%  
    Number of Slices containing only related logic 42 42 100%  
    Number of Slices containing unrelated logic 0 42 0%  
Total Number of 4 input LUTs 71 9,312 1%  
    Number used as logic 38      
    Number used as a route-thru 33      
Number of bonded IOBs 33 232 14%  
Number of RAMB16s 2 20 10%  
Number of BUFGMUXs 2 24 8%  
Average Fanout of Non-Clock Nets 2.31      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 7 23:28:03 2011089 Warnings (0 new)1 Info (0 new)
Translation ReportCurrentWed Dec 7 23:28:08 2011000
Map ReportCurrentWed Dec 7 23:28:17 2011025 Warnings (0 new)2 Infos (0 new)
Place and Route ReportCurrentWed Dec 7 23:28:31 2011002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Dec 7 23:28:33 2011005 Infos (0 new)
Bitgen ReportOut of DateWed Dec 7 10:08:52 2011025 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateWed Dec 7 10:34:48 2011
WebTalk Log FileOut of DateWed Dec 7 10:35:04 2011

Date Generated: 12/07/2011 - 23:32:16