LabF_count Project Status (11/21/2010 - 22:36:20) | |||
Project File: | LabF_count.ise | Implementation State: | Programming File Not Generated |
Module Name: | musicbox |
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No Errors |
Target Device: | xc3s500e-5fg320 |
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21 Warnings |
Product Version: | ISE 11.1 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 100 | 9,312 | 1% | ||
Number of 4 input LUTs | 155 | 9,312 | 1% | ||
Number of occupied Slices | 100 | 4,656 | 2% | ||
Number of Slices containing only related logic | 100 | 100 | 100% | ||
Number of Slices containing unrelated logic | 0 | 100 | 0% | ||
Total Number of 4 input LUTs | 186 | 9,312 | 1% | ||
Number used as logic | 155 | ||||
Number used as a route-thru | 31 | ||||
Number of bonded IOBs | 7 | 232 | 3% | ||
Number of RAMB16s | 16 | 20 | 80% | ||
Number of BUFGMUXs | 3 | 24 | 12% | ||
Average Fanout of Non-Clock Nets | 2.34 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sun Nov 21 23:00:52 2010 | 0 | 21 Warnings | 0 | |
Translation Report | Current | Sun Nov 21 23:01:09 2010 | 0 | 0 | 0 | |
Map Report | Current | Sun Nov 21 23:01:31 2010 | 0 | 0 | 2 Infos | |
Place and Route Report | Current | Sun Nov 21 23:02:08 2010 | 0 | 0 | 3 Infos | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Sun Nov 21 23:02:13 2010 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | Sun Nov 21 23:04:12 2010 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated |