Below is a brief description of some of my recent research projects
Energy Efficient Synchronization Techniques for Embedded Architectures
Because many embedded devices run on batteries, energy efficiency is perhaps the single most important criterion for evaluating hardware and software effectiveness in embedded devices. In this project, we evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. We focus on providing simple hardware accelerators for common software synchronization patterns found in embedded systems. These hardware accelerators so far have included a simple hardware transactional memory implementation and hardware semaphores. A careful balance of complexity, hardware, and software balancing is important in order to adhere to the tight performance, power, and area constraints set by embedded systems.
Timing Analysis and Verification Tool Development
Accurate delay modeling is critical for estimating performance of circuits once they are fabricated. However, there are a number of difficult-to-model factors that influence delay, including number of inputs simultaneously switching and crosstalk, that make correlation between pre- and post-silicon delay measurements hard to achieve. In this research project, we are developing a timing analysis tool that integrates a data-dependent delay model into its analysis. The main idea is to estimate the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a Boolean satisfiability solver. The goal is to develop a fast simulation tool that can be applied at design time with delay estimates that correlate more closely with actual delays measured from the fabricated circuit. We are also looking into other problems related to timing analysis and its role in debugging microprocessor chips.
Using Identified Circuit Invariance for Online Error Detection
Detection and correction of errors is becoming increasingly critical as integrated circuits scale to smaller feature sizes and become more susceptible to a host of problems caused by process variations, defects, operational influences and environmental influences. Ensuring reliable computation at the nanoscale thus requires mechanisms to detect and correct errors during normal circuit operation. This project explores methodology for automatically designing efficient online error detection logic for circuits based on the identification of invariant relationships. In our approach these invariant relationships are characterized as logic implications. Logic implications have been targeted to many different applications including area/delay optimization, peak current estimation, false noise analysis, determining redundant and untestable faults, efficient ATPG, and identifying illegal states. Yet, checking for implication violations can be a very powerful approach for error detection. The novel contributions of this project lie primarily in the efficient identification of those implications that are most valuable for error detection and in the incorporation of those implications into the low-overhead error-checking hardware. Our approach is applicable for detecting static, dynamic, and delay faults generated from single-event upsets or missed manufacturing defects.
Probabilistic Devices and Architectures for Nanoscale Computation
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit operation characterized by lower supply voltages VDD and smaller device sizes. Both of these downscaling approaches reduce the margin of immunity to thermal noise, alpha particle strikes, and threshold voltage variations. In this work, we explore a probabilistic methodology for designing nanoscale devices and architectures based on Markov Random Fields (MRF). The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. We have demonstrated that our MRF approach provides superior noise immunity for circuits that operate under highly noisy conditions. A key focus of this work is improving area overhead in the implementation of these circuits and conducting an in-depth analysis of the expected error rates in ultimate CMOS circuits.