Ruth Iris Bahar
Associate Professor of Engineering:
Engineering
Phone: +1 401 863 1430
Ruth_Bahar@Brown.EDU
Iris Bahar's research interests lie broadly in the areas of computer architecture, electronic design automation, and digital circuit design. In particular, she is working on developing new approaches to reduce power dissipation and improve reliability in high-performance processors, including multiprocessors and nanocomputing systems. In addition, she is working on methods to improve the accuracy of timing analyzers used for verifying circuits designs.
Biography
R. Iris Bahar received the B.S. and M.S. degrees in computer engineering from the University of Illinois, Urbana-Champaign, and the Ph.D. degree in electrical and computer engineering from the University of Colorado, Boulder. Before entering the Ph.D program at CU-Boulder, she was with Digital Equipment Corporation, responsible for the hardware implementation of their latest processor. In 1996 she joined the Division of Engineering, Brown University, as an Assistant Professor. In 2003 she was promoted to Associate Professor. She is a recipient of the National Science Foundation CAREER award. Her research interests include computer architecture; computer-aided design for synthesis, verification and low-power applications; and design, test, and reliability issues for nanoscale systems.
Interests
The following is a summary of Iris Bahar's reserch projects:
1. "Accurate Timing Analysis using Pattern-Dependent Delay Models and Boolean Satisfiability Analysis" (in collaboration with Intel Corporation)
Accurate delay modeling is critical for estimating performance of circuits once they are fabricated. However, there are a number of difficult to model factors that influence delay, including number of inputs simultaneously switching and crosstalk, that make correlation between pre- and post-silicon delay measurements hard to achieve. In this research project, we are developing a timing analysis tool that integrates a data-dependent delay model into its analysis. The main idea is to estimate the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a Boolean satisfiability solver. The goal is to develop a fast simulation tool that can be applied at design time with delay estimates that correlate more closely with actual delays measured from the fabricated circuit.
2. "Using Identified Circuit Invariance for Online Error Detection"
Detection and correction of errors is becoming increasingly critical as integrated circuits scale to smaller feature sizes and become more susceptible to a host of problems caused by process variations, defects, operational influences and environmental influences. Ensuring reliable computation at the nanoscale thus requires mechanisms to detect and correct errors during normal circuit operation. This project explores methodologies for automatically designing efficient online error detection logic for circuits based on the identification of invariant relationships. In our approach these invariant relationships are characterized as logic implications. Checking for implication violations can be a very powerful approach for error detection, and in our preliminary work we have found that significant error coverage is possible, even with only a 10% area overhead (see list of work under review). Our approach is applicable for detecting static, dynamic, and delay faults generated from single-event upsets or missed manufacturing defects.
3. "Probabilistic Devices and Architectures for Nanoscale Computation"
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. In this work, we explore a probabilistic-based design methodology for designing nanoscale devices and architectures based on Markov Random Fields (MRF). The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. We have demonstrated that our MRF approach provides superior noise immunity for circuits that operate under highly noisy conditions. This projects also analyzes expected error rates for ultimate CMOS circuits due to thermal noise, alpha particle strikes, and threshold voltage variation.
4. "Energy Efficient Synchronization Techniques for Embedded Architectures"
Because many embedded devices run on batteries, energy efficiency is perhaps the single most important criterion for evaluating hardware and software effectiveness in embedded devices. In this project, we evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. We focus on providing simple hardware accelerators for common software synchronization patterns found in embedded systems. We are also considering applications that employ concurrency patterns based on conditional synchronization, or semaphores, such as pipelines and barriers. We have proposed a novel energy-efficient hardware semaphore construction in which cores spin on local scratch-pad memory, reducing the load on the shared bus, thereby reducing energy consumption.
Awards
NSF Early Career Development (CAREER) Award, 1998.
Patricia Robert Harris Fellowship to support graduate studies, 1992–1995.
Eta Kappa Nu, Electrical Engineering Honor Society, since 1985.
Tau Beta Pi, Engineering Honor Society, since 1985.
Affiliations
Institute of Electrical and Electronic Engineers (IEEE)
Association of Computing Machinery (ACM)
Teaching
Professor Bahar's teaching interests include courses on computer architecture, integrated circuit design, electronic design automation, and nanocomputing (or how to effectively design computing systems using various emerging nanotechnologies).
Funded Research
Current Grants:
1. National Science Foundation Grant under Nanotechnology Interdisciplinary Research Teams (NIRT) entitled "NIRT: Fault-tolerant, Probabilistic Computing with Markov Random Field Architectures and CMOS Nanodevices" Principal investigators: R. Iris Bahar, Joseph Mundy, William Patterson, and Alexander Zaslavsky. Award date: September 2005. Award amount: $317,000 over 4 years.
2. Intel Corporation grant entitled "Fast, Accurate Symbolic Timing Analysis for Custom Circuits." Principal investigator, R. Iris Bahar. Award date: October 2005. Award amount: $50,000 over 2 years.
Completed Grants:
1. Undergraduate Teaching and Research Assistantship for a collaborative project with Brad Simeral. Project title: "Computer System Design Laboratory: Building Systems Using Today's Technology." June–August 1997. Award amount: $2,200.
2. Design Automation Graduate Scholarship entitled "Using Implications to Drive Low-Power Optimization of Technology-Dependent Circuits," sponsored by the Design Automation Conference. 9/97–5/98. Award amount: $12,000.
3. Richard B. Salomon Faculty Research Award for project entitled "Low-Power VLSI: Designs for the Future." 9/97–5/98. Award amount: $14,500.
4. National Science Foundation Professional Opportunities for Women in Research and Education (POWRE) award entitled "Integration of Non-Conventional CMOS Structures into Fully-Automated Synthesis Tools." Principal investigator, R. I. Bahar. 9/98–5/00. Award amount: $75,000.
5. National Sciencde Foundation Early Career Development Grant (CAREER) proposal entitled "(Re)Configurable Architectures for High Performance and Low Power." Principal investigator, R. I. Bahar. 6/98–5/03. Award amount: $214,000.
5. Microsoft Grant for Teaching and Research. The goal of this grant was to become familiar with Windows-based real-time operating systems by using it for operating a life-like robotic head for speech recognition experiments. Principal investigators, R. I. Bahar and H.
Silverman. Award date: June 2003. Award amount: $25,000 over 1 year.
6. Microsoft Grant for Course Development. This grant was used to purchase and test out new Windows-based layout tools for EN160 (VLSI System Design). Principal investigator, R. I. Bahar. Award date: August 2003. Award amount: $5,000 over 1 year.
7. National Science Foundation Grant in the area of Nanotechnology Exploratory Research entitled "NER: Y-Junction Nanotube-based Computer Devices and Architectures" Principal investigators, R. Iris Bahar, Jie Chen and Joseph Mundy. Award date: July 2003. Award amount: $100,000 over 2 years.
8. Collaborative Research Award from SUN Microsystems, Inc. "Expanding Teaching and Research Activities in VLSI System Design and Computer Architecture." Principal investigator,R. I. Bahar. Award date: December 2000. Award amount: Over $300,000 worth of equipment.
9. National Science Foundation Grant in the area of Design Automation entitled "Using Symbolic DC Analysis to Evaluate Complex Custom Circuit Designs." Principal investigator, R. I. Bahar. Award date: July 2002. Award amount: $160,000 over 3 years.
10. National Science Foundation Grant in the area of Computer Systems Architecture entitled "Combining Hardware and Software Monitoring for Improved Power and Performance Tuning" Principal investigators, R. I. Bahar and R. Weiss. Award date: August 2003. Award amount: $160,000 over 3 years.
11. National Science Foundation Grant under Nanotechnology Exploratory Research entitled "NER: Exploring Nanodevices for Probabilistic Computing Architectures." Principal investigators: Alexander Zaslavsky, R. Iris Bahar, Jie Chen and Joseph Mundy. Award date: August 2004. Award amount: $100,000 over 2 years.
12. Undergraduate Teaching and Research Assistantship (UTRA) for a collaborative project with Briant Mairs and Prof. Jennifer Dworak entitled "Redundant Circuitry Generation using Fault Tolerance Testing Tools" June–August 2007. Award amount: $2500.
