(a) If inputs are either 0 or 1, how many different output levels are possible?
(b) If inputs can now be -1, 0, or +1, how many different output levels are possible?
What are the maximum and minimum values with 3 possible inputs?
1. Suppose 7 numbers are represented by a 4-bit grey code:
0000 0
0001 1
0011 2
0111 3
1111 4
1110 5
1100 6
1000 7
Can you think of a way for a D!A converter to convert the grey code into the voltages which
the codes represent? Hint: You can use the multiplication operator.
from TIMING S4 -- switch de-bouncing using comparators for better intro problem...
2. A summation amplifier is connected to three discrete inputs di through weights, wi:
(a) If inputs are either 0 or 1, how many different output levels are possible?
(b) If inputs can now be -1, 0, or +1, how many different output levels are possible?
What are the maximum and minimum values with 3 possible inputs?
3. Find the best match for the following analogy: digital is to analog as
(a) seconds are to minutes
(b) jigsaw pieces are to finished jigsaw puzzle
(c) pixel is to picture
(d) tree is to forest
(e) drips are to a puddle
4. What is VOUT in the following circuit?
5. An "ideal" 8-bit D-A converter spans a range from 0 to 2.55 volts;
What is the resolution of the converter?
6. Why would it work to prevent saturation in an op amp used as a DAC to make sure that when only the MSB is HI the op amp output is less than half the saturation voltage?
7. Draw a circuit diagram for a 1-bit DAC, which spans the range from 0 to 4 volts.
8. A linear multiplying 4-bit DAC has an output AOUT as shown in the table below. For the
other inputs listed, what are the expected analog outs?
VREF DIN AOUT
1.0 1000 2.0v.
(a) 1.0 0100 ?
(b) 2.0 0010 ?
(c) -3.0 0110 ?
(d) 1.5 1001 ?
(e) -2.0 1111 ?
9. What is the output of the 4-bit multiplying DAC shown below?
The analog switches choose between the VREF rail and the ground rail. The input is 0110.
The op amp is a negative gain summation amplifier.
10. What should the thresholds qL, qH, and the flip flop inputs (X, Y) be for the analog
comparators and SR flip flop below in order that the circuit exhibit the inverter hysteresis
shown at the right?
11. DAC linearity. Suppose the actual weights of a 4-bit DAC are 8, 3.6, 2.2, 1.0, instead of
the ideal weights 8, 4, 2, 1. The output VOUT is 1.0 volts when the digital input is 0001.
Assume there is no offset when the input is 0000.
(a) Graph VOUT as a function of the 16 digital inputs. On the graph show what the expected
output is for ideal values of weights.
(b) What is the maximum amount of non-linearity that the deviant DAC shows on its
input-output curve?
12. What if, not un-reasonably, we want 8 bits of digital input to be resolved into 28 = 256
levels of analog output? By the scheme so far presented, we would need a set of 8 resistors,
say 1K, 2K, 4K, etc, on up to 128K, a tough set to deal with. For one problem, it's not
possible to make resistors that differ by a factor of 128 on the same IC substrate, For
another problem, it means that even if you're going to build a discrete DAC you have to
find and stock 8 different precision resistors, in uncommon sizes.
Here's another solution, the R-2R ladder, shown here in a 4-bit version.
It uses twice as many resistors as the power-of-2 version, but only 2 sizes are needed!
(a) Use linear superposition to analyze the ladder for the simplest case, two inputs: First
assume IN2 = 0 and IN1 = 1. We're interested in the current ifinal that flows through the last
2R. (The DAC op amp is really just trying to sum up currents created by Vin / Rs .)
Current coming out of the MSB resistor divides at the R-2R junction. Consider a piece of
the ladder:
Two equal resistors in parallel have an effective resistance of R/2. Twice as much current
flows through ifinal thanks to MSB, as (in this case) through/from LSB.
WHAT'S THE QUESTION?!
With the R-2R ladder you only need to stock two sizes of resistor, differing by a power
of two...but you need twice as many.
An Analog Devices 7524 DAC uses an R-2R with 10K and 20KW.
13. *Design an analog comparator using a summation amplifier. The comparator will have two
inputs--analog unknown and threshold. If analog-unknown > threshold then
comparator output will be logical HI, otherwise it will be logical LO.
[need some way to limit output to logical HI = 5v and logical LO = 0v, or use CMOS, which can
tolerate high input voltages]
problem on DAC speed for raster scan.
14. Counting ADC. Study the counting converter below. When the digital input of the internal
DAC is 0001, its analog output is 1.0 volts.
(a) What range should AIN have in order that all 16 of the counter outputs can represent
possible sub-ranges of AIN?
(b) What is the maximum amount of time to convert the largest AIN? (The clock is 1KHz.)
(c) Should INHIBIT assert HI or LO?
(d) Design a start-of-conversion sub-circuit so the counting converter will return one
digital number after being presented with a SOC pulse.
15. In the 4-bit counting AD converter in S3/6, and shown above,
(a) How can you insure that the counter state 0000 is a possible output, and that no value
of AIN is more than 1 LSB in error?
(b) What would happen if a down-counter instead of an up-counter were used? Would
the circuit still stop on a correct answer?
16. Show how to hook up an analog comparator to mimic a TTL inverter.
17. Draw out the circuit diagram for a 3-bit flash converter, using 7 analog comparators. Arrange the resistor ladder so that low-end staircase error is minimized.
18. An 8-bit sub-ranging flash AD converter, diagrammed below, is required to make 100
level resolution (2 digit decimal) conversions. The sub-components are two 10 level
resolution flash converters. The reference voltage for the upper flash converter is 12.00
volts, which is greater than the largest possible AIN. What should be the reference on the
lower flash converter in order for the system to work properly, and give digital answers
which can appear in 2-digit BCD?
19. You are given two 4-bit successive approximation AD converters,
(a) How can you hook the two up in a sub-ranging circuit to make an 8-bit conversion?
Assume the Analog input ranges from 0 to 6 volts.
Hint: You need to choose VREF and the SOC rate on each 4-bit converter, to be
compatible with the full 8-bit conversion.]
(b) Will the sub-ranging SA circuit be faster or slower than a regular 8-bit SA converter
hooked to the same clock as the sub-ranging converter?
20. Suppose, for a range from AIN-min to AIN-max, we need an ADC which presents 100 levels of digital output, in a 2-digit BCD code. With a counting or SA ADC as a start, show how such a 2-digit ADC could be designed. Such a circuit is needed in digital multi-meters, with their decimal displays.
21. The successive approximation D-A converter requires a sequencer which cycles 1 active
bit around a shift register. For a 4-bit SA converter, design such a sequencer, which will
start up automatically and be immune to noise which may cause a bit to change from 0 to
1 or 1 to 0. Start your design with a serial-in, parallel-out shift register. Simply sending
the last parallel output bit back around to the serial in is not satisfactory.
[Hint: make a truth table whose output is serial in and whose inputs are the various parallel
outputs.]
22. A certain 4-bit digital to analog converter is governed by the equation
The designer had hoped his the gain of the amplifier would have given weights of 1, 2, 4,
8, instead of the 10% greater gains shown.
A designer attempts to correct for the full-scale error by subtracting a 0.3 offset term,
(a) At digital input of 1111 how much is error reduced by the offset?
(b) Is either the original expression for AOUT or the offset function AOUT' a linear function?
23. The Analog Devices Analog-Digital Conversion Handbook defines code width of a ADC
as "The range of analog input value over which a given digital output will occur." Shown
below is a 4-bit successive approximation ADC, with non-standard gains on each of the
inputs to the internal summation amplifier.
(a) What is the code width for 0011? For 0000?
where the absolute range of AIN is 0 volts to 20 volts.
(b) Graph the transitions which the ADC output makes, as a function of AIN.
24. In an 8-bit sub-ranging flash converter, shown below, (a) What relationship must exist
between the upper and lower reference voltages in order for the answer to appear in natural
binary code?
(b)
25. A certain 3-bit ADC, which contains a DAC, has the following input-output relationship:
What are the weights on the the three DAC inputs? [they're not 1-2-4!]
26. An 8-bit successive approximation ADC must acquire a new analog value every 12 msec.
(SOC pulse every 12 msec.) (a) How fast must the internal clock on the ADC go to
accommodate this data acquisition rate? State any assumptions you need to about the
internal cycles of the SA registers.
(b) If the ADC were 12 bit instead of 8 bit how would the answer to (a) change?
* (c) According to the sampling theorem, to avoid aliasing of the digital output, the
maximum frequency component on the analog input must be less than � the sampling
rate. What is the maximum frequency component of input allowed for the 8-bit conversion
process in (a) ?
27. * Here is the delta modulator tracking converter circuit again.
If you know that AIN started at 0.0 volts, can you devise a circuit which will reconstruct the
analog waveform from the serial bit stream? Hint: Same clock will be used in both circuits.
28. * Let an analog input be described completely by a Fourier series of
(a) What is the highest frequency component in AIN(t), expressed in Hz?
(b) How many samples per second are required in order to reconstruct AIN(t)? Assume that
an 8-bit resolution is satisfactory for reconstruction. [Hint: How many unknowns are in the
expression for AIN(t) ?]
29. A 3-bit successive approximation A-D converter has 3 flip flops which control 3 inputs
to an internal DAC. Logic in the SA circuit controls when the flip flops are set or reset. Shown
below are assertions of SET and RESET for each of the three flip flops.
What is the digital answer represented by the waveforms above?
What would the waveforms look like if the answer were 000? if it were 111?
30. An 8-bit successive approximation analog-to-digital converter must make 1000 conversions per second. What should be the rate on the internal clock?
31. A 3-bit A-D converter can have the "ideal" analog-digital relationship shown in the figure
below,
Shown below are four other possibilities:
Which of the above deviations from ideal is caused by
Linearity error
Offset error
Missing codes
non-linear scale factor error?
32. A voltage-controlled oscillator (VCO) is governed by the relationship
freq = (V+1)�100,
where freq is the pulses/sec output and V is the magnitude of the voltage input. Assume
0<V<5 and that V changes slowly with respect to the output pulse rate.
Assume AIN is applied to the VCO, and the VCO output is sent to a 12-bit counter. After
a reset pulse (SOC) which makes the counter output 0000 0000 0000, the counter is
allowed to tally VCO pulses for 1 second, at which time its output is latched.
(a) Draw a circuit which show the arrangement of components for the frequency-to-time
ADC described above.
(b) What will the count, in hex, be, if AIN = 1.4 volts for the entire 1 second of counting?
(c) Is the V-f converter described here linear?
33. What's the "dual slope" in a dual slope AD converter?
34. A dual-slope AD converter has a VREF of -2 volts, and an integrator with the following
form, 
. The counter see pulses coming in at a rate of 100/sec. VREF is
selected by a control line. After the 0.75 sec of positive AIN integration, the switch selects
VREF. VREF is integrated until the output of the integrator crosses 0 volts, at which time the
answer from the counter is latched.
If AIN = +1.2 volts, what will be the final count? Express your answer in hex.
35. In hooking up a counting ADC, the builder inadvertently switched the connections of the
the LSB and the second LSB counter bits to the DAC inputs.
(a) Graph AIN vs digital out, for the eight possible codes
(b) Are any codes missing in the ADC output?
(c) Is your answer to (a) and (b) any different if a successive approximation ADC is involved,
and the LSB, next LSB bits to the DAC are again reversed from the flip flop controllers?
36. **Voltage-to-Time converter. A modification of the Dual Slope scheme can give us
another kind of A-D converter. Suppose we integrate Ain, and compare the integration with
-Vref. Until we reach -Vref we have a down counter in action. Whatever the counter gets
to in the time it takes Vout = 1/RsC Vin dt to reach -Vref, is the answer. Counter must be
reloaded to start over.
(Does this action give us a period-to-frequency converter? no...)
Can also reverse the roles of Ain and Vref, and count up (Taub & Schilling, p. 535)
What about controlling the shift on a register? What should be loaded?
1000 0000 0000. Then, however far down-shifted, does it represent a frequency?...
37. The code words of a particular ideal A-D converter have an inherent uncertainty of 1/32 FSR (full scale range). What can be done to the converter to decrease the uncertainty to 1/128 FSR?
38. A 3-bit SA ADC has the timing waveforms shown below
(a) How many conversions per second can be made?
(b) What is the output of the system during the bold lines on the clock waveform?
(c) What (and when) should be used to generate an EOC signal?
39. Listed below are seven types of of ADC discussed in this �
Counting converter
Flash converter
Sub-ranging flash converter
Successive approx.
Tracking
Voltage-to-frequency
Dual slope converter
(a) Which of these have an internal DAC?
(b) Which have analog comparators?
(c) Which have digital counters?
40. Assume an 8-bit resolution ADC works over the range 0-10.24 volts.
Suppose it has an output of 1001 0111 over the input range 5.92 - 5.96 v,
[assume the range of the code word 0000 0000 is 0-40mV (not 0-20mV)]
What is its absolute accuracy error at the code word 1001 0111 ?
41. In A-D converter specifications for amplitude, resolution and accuracy can be
distinguished. Select the best match for the following analogy:
Resolution is to accuracy as
(a) speed is to velocity
(b) distance is to location
(c) melody is to rhythm
(d) advertisement is to product.