2901, registered ALU, S5-197
2910
instruction set, S5-208
microprogram sequencer, width of address bus, S5-202
3-input NAND gate, open collector output, S1-26
3-state, propagation delays, t-PZL, t-PZH, t-PLZ, t-PHZ, S2-54
311, analog comparator, open collector output, S3-89
555
front end, S3-91
used as a 1-shot, S4-160
654, voltage controlled oscillator, Analog Devices, S3-100
7406, open collector inverter, S1-26
74123, dual 1-shot circuit, S4-160
7414, Schmitt trigger inverter, S1-43
74157, timing parameters, S2-54
7448, 7-segment display driver, S2-58
74LS240
3-state buffer, S1-34
3-state inverter, S1-50
7524
8-bit multiplying DAC, S3-84
Analog Devices DA converter, with R-2R ladder, S3-114
absolute maximum ratings, S1-16
AC characteristics, of chip parameters, S2-51
accuracy
in DA converters, S3-85
of analog to digital conversion, S3-104
address generator, in micro programmed control, S5-200
aluminum spiking, in temperature degradation, S2-60
analog to digital converter, S3-87-S3-92
asynchronous, circuits, S4-124
Babbage, and his difference engine, S1-1
BiCMOS, logic family, S2-65
brain, S2-70
bus, S1-32
bypass capacitor, S1-31
capacitor, as voltage-change sensitive switch, S4-156
CMOS
a super-family of logic, S2-61
complementary metal oxide semiconductor, S2-63
code width, S3-103
in A-D conversion, S3-116
comparator, analog, S3-89, S4-142
critical path, in timing, S2-55
current parameters, for computing fanout, S1-17
cycle
in asynchronous circuit, S4-152
in asynchronous design, S4-134
Darlington output, S1-48
DC characteristics, of chip parameters, S2-51
delay-power product, S2-59
delta modulator, S3-99
diamond, crystal form carbon, S2-71
differentiation, operation by CR circuit, S4-156
digital to analog converter, multiplying, S3-83
diode logic, obsolete logic family, S2-61
dual-slope A-D converter, S3-101
ECL 100K, emitter coupled logic family, S2-68
electronic lock, S4-163
emitter-coupled logic, S2-65
end of conversion, EOC, for A-D converter, S3-88
energy, S2-56
error, offset, in DACs, S3-82
fan-out, S1-20
fanout, dynamics, S1-22
field programmable gate arrays, FPGAs compared to logic families, S2-70
finite state machine, S4-134
flash converter, A-D, S3-91
flash converter, sub-ranging, S3-94
flow table, primitive, S4-132
full scale range, S3-103
fundamental mode, for asynchronous circuits, S4-125
gain, of op amp, with virtual ground, S3-78
gallium Arsenide, GaAs, S2-65, S2-67
ground state, in async design, S4-141
h - FE, current gain of a transistor, S1-48
high-pass filter, in 1-shot design, S4-156
hysteresis, S1-14
in analog comparators, S3-89-S3-91
I-IH, high level input current, S1-17
I-IL, low level input current, S1-17
I-OH, high level output current, S1-17
I-OL, low level output current, S1-17
impedance, input, S1-18
input resistance, of an inverter gate, S1-5
instruction, different levels of, S5-209
interface, in asynchronous circuits, S4-125
inverter, S1-4
I/O curve of, S1-3-S1-5
JSR, jump to subroutine, S5-203
key-in-lock
informal async design, S4-125
informal asynchronous design method, S4-128
Kirchoff's Current Law, S3-78-S3-79
last-in, first-out, register stack, LIFO, S5-205
lava lamp, demonstration of non-periodic oscillator, S2-74
leakage current, S1-29
linear function, S3-75
logic family, S1-2, S2-61
mapping ROM, in microprogramming, S5-201
Mealy circuit, in asynchronous design, S4-129
Memory address register, S5-210
merger table, for async design, S4-135
merging, of primitive states, in asynchronous design, S4-134
metastability, S1-11
metastable state, on I/O graph, S1-9
micro-instruction, in microprogramming, S5-199
microprogramming, S5-199-S5-207
military, parts designated by 5400 TTL series, S2-62
MOS, S2-63
nested subroutines, in microprogram sequencer, S5-205
neuron, S3-76
noise margin
high-level, S1-13
low-level, S1-13
off-state output current, of a 3-state device, S1-34
one-shot, S4-154
open-collector output, S1-24-S1-25
operational amplifier, S3-78
packing density, of gates per chip, S2-68
PACMAN, S4-175
parasitic junction capacitance, as a source of t-Prop, S2-52-S2-53
pipeline register, S5-201
power dissipation, dynamic, S2-59
primitive flow table, S4-132
primitive state, in asynchronous design, S4-131-S4-132
priority, S4-159
propagation delay, S2-51-S2-52
pull-up resistor, S1-24
pulse mode
for asynchronous circuits, S4-126
restriction on asynchronous input, S4-165
pulse-stretcher, S4-155
R-2R ladder, S3-113
race, S4-152
critical, S4-152
resistor, in DAC, S3-84
resistor-transistor logic, obsolete logic family, S2-61
resolution, of D to A converter, S3-85
RISC, = reduced instruction set computer, S5-221
rise time, S2-52
RTS, return from subroutine, S5-203
sample and hold, S3-106
sampling theorem, S3-107
saturation, S1-38
of an ON transistor, S2-52
of op amp output., S3-80
Schmitt trigger, S1-15
Schottky diode, for speed in improvement in TTL, S2-53
sequencer, in succ. approx design, S3-96
settling time, in DA converters, S3-86
splitter, S1-29
start of conversion, SOC, for A-D converter, S3-88
state
for asynchronous circuit, S4-127
transient, or unstable, S4-134
subroutining, in a microprogram sequencer, S5-203
successive approximation, D-A converter, S3-95, S3-96-S3-97
superposition, and linear functions, applied to DACs, S3-75
supply current, for a chip, S2-57
switch, analog, for use in DAC's, S3-82
Switching speed, S2-51
synchronicity, concept of Jung, S4-193
t-PHL, propagation time, high to low, S2-54
t-PLH, propagation time, low to high, S2-54
t-REC, recovery time, in flip flops, S2-55
t-W, minimum width of SET or RESET pulse is SR flip flop, S2-55
timing diagram, for asynchronous design, S4-128
tracking converter, A-D, S3-99
transparent latch, S4-185
TTL, a super-family of logic, S2-61
TTL gate, input, S1-36
V-IH, S1-9
V-IL, S1-9
V-OH, S1-10
V-OL, S1-10
VCO, voltage controlled oscillator, S3-99
vector ROM, for interrupts, S5-207
Vending machine, asynchronous design, S4-191
voltage-to-frequency converter, S3-99
window discriminator, asynchronous design, S4-142
wired AND, S1-46
wired logic, with open collector outputs, S1-25
Yeats, WB, S5-194