Brown University School of Engineering

Computer Engineering Seminar "Defect Tolerant Logic Implementation on Nano-crossbar Architectures"

Add event to my Google calendar Add event to my Google calendar Share this event on facebook E-mail this event
Thursday, May 16, 2013 11:00am - 12:00pm

Title: Defect Tolerant Logic Implementation on Nano-crossbar Architectures Speaker: Professor Wenjing Rao, University of Illinois, Chicago Date and Location: Thursday May 16, 2013, 11:00 AM -12:00 PM, B&H 190 Abstract: Future systems based on nanoscale devices will enjoy great potential in parallelism, yet at the same time face significant reliability challenges. This talk focuses on dealing with the challenges of implementing two-level logic functions onto a particular crossbar architecture, which has been shown to be highly promising for future nanoelectronic systems. Due to the self-assembly fabrication process, massive defects are inevitable, thus imposing the reliability challenge: testing and discarding defective crossbars will no longer be affordable; the target logic functions have to be somehow implemented onto nanocrossbars with a high number of defects, possibly through a post-manufacturing reconfiguration phase. Basically, the defect occurrences introduce irregular topological constraints onto the otherwise regular structure of the crossbar architecture. Therefore, it is possible to tolerate, or even "utilize" the defects, via a mapping process. Essentially, the mapping process exploits the freedom of choosing which variables / products (in the logic function) to map to which of the vertical / horizontal wires (in the crossbar). This talk will cover the modeling of the logic mapping framework, some initial analytical metrics for runtime and yield, and two defect tolerance approaches that can help improve the mapping success rate significantly: 1) a "logic morphing" approach that exploits various equivalent logic forms, and 2) a "hardening" scheme that employs hardware redundancy to make the target logic function inherently more defect tolerant. These three approaches (mapping, morphing, and hardening) exploit orthogonal dimensions of freedom, and can be simultaneously carried out in an integrated algorithmic framework, providing an efficient solution for defect tolerant nanocrossbar-based architectures. BIO: Wenjing Rao received her PhD in the Department of Computer Science and Engineering of UCSD in 2008, and is currently an assistant professor in the Electrical and Computer Engineering Department of UIC. Her research interests include defect / fault tolerance and new computational paradigm of nanoelectronic systems, VLSI test, and reliability. Host: Professor Sherief Reda, School of Engineering.