Brown University School of Engineering

The HW/SW Interface Seminar Series: Jointly Sponsored by Engineering and Computer Science

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Monday, October 02, 2017 12:00pm - 1:00pm

Xuehai Qian, Dept. of Electrical Engineering and Computer Science at the University of Southern California, will present a talk: "Efficient Graph Processing with Cross-Stack Co-Design". Abstract: Graph analytics has emerged as an important way to understand the relationships between the heterogeneous types of data, allowing data analysts to draw valuable insights. In graph processing, edges connected to a vertex are stored sequentially but accessing vertices (i.e., neighbors) leads to the random memory accesses with poor locality. Due to the simple computations on the accessed vertices, memory bandwidth requirement is high. Naturally, graph processing could benefit from processing-in- memory (PIM), which greatly reduces data movements. Moreover, to improve convergence speed of iterative graph algorithms, fundamental algorithm enhancement is required. In this talk, I attempt to demonstrate the effectiveness of cross-stack codesign for graph processing. First, I will present GraphCube, a graph processing architecture/runtime based on Hybrid Memory Cube (HMC) that supports batched regular inter-cube communication and streamlined intra-cube memory accesses. Second, I will present GraphP, another HMC-based graph processing system with co-designed graph partition and programming model to drastically reduce inter-cube communication. Third, I will present Wonderland, an out-of- core graph processing system based on graph abstraction. With approximate graph information encoded, graph abstraction can accelerate convergence by producing better initial results, enabling faster information propagation and better scheduling. Bio: Xuehai Qian is an assistant professor at the Ming Hsieh Department of Electrical Engineering and the Department of Computer Science at the University of Southern California. He has a Ph.D. from the Computer Science Department at University of Illinois at Urbana-Champaign. He has made contributions to parallel computer architecture, including cache coherence for atomic block execution, memory consistency check, architectural support for deterministic record and replay. His recent research interests include system and architecture acceleration for graph processing and machine learning, Non-Volatile Memory (NVM) system and applications of emerging technology.