Jannaty P, Sabou FC, Le ST, Donato M, Bahar IR, Patterson W, et al. Shot-Noise-Induced Failure in Nanoscale Flip-Flops. IEEE Transactions on Electron Devices. 2012;59:800-6.
Li H, Mundy J, Patterson WR, Kazazis D, Zaslavsky A, Bahar IR. Prediction of soft errors in nanoscale CMOS circuits. In: Nanoelectronic Devices for Defense & Security (NANO-DDS) Conference. Arlington, VA; 2007.
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. In: Proceedings of the conference on Design, automation and test in Europe. San Jose, CA, USA: EDA Consortium; 2007. p. 576-81. (DATE '07).
Li H, Mundy J, Patterson W, Kazazis D, Zaslavsky A, Bahar IR. Thermally-induced soft errors in nanoscale CMOS circuits. In: Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures. Washington, DC, USA: IEEE Computer Society; 2007. p. 62-9. (NANOARCH '07).
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Designing {MRF} based Error Correcting Circuits for Memory Elements. In: IEEE/ACM Design Automation and Test in Europe Conference. Munich, Germany; 2006. p. 1-2.