Dworak J, Nepal K, Alves N, Shi Y, Imbriglia N, Bahar IR. Using Implications to Choose Tests Through Suspect Fault Identification. ACM Transactions on Design Automation of Electronic Systems (TODAES). 2013;18:14:1-14:19.
Alves N, Shi Y, Dworak J, Bahar IR, Nepal K. Enhancing online error detection through area-efficient multi-site implications. In: VLSI Test Symposium (VTS), 2011 IEEE 29th.; 2011. p. 241-6.
Alves N, Buben A, Nepal K, Dworak J, Bahar IR. A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2010;29:788-801.
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. In: Proceedings of the conference on Design, automation and test in Europe. San Jose, CA, USA: EDA Consortium; 2007. p. 576-81. (DATE '07).
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Techniques for {MRF} based implementation of multi-level combinational circuits. In: Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH 2006). Boston; 2006.
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Optimizing noise-immune nanoscale circuits using principles of Markov random fields. In: Proceedings of the 16th ACM Great Lakes symposium on VLSI. New York, NY, USA: ACM; 2006. p. 149-52. (GLSVLSI '06).
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Designing {MRF} based Error Correcting Circuits for Memory Elements. In: IEEE/ACM Design Automation and Test in Europe Conference. Munich, Germany; 2006. p. 1-2.
Song HY, Nepal K, Bahar IR, Grodstein J. Timing Analysis for Full-Custom Circuits Using Symbolic {DC} Formulations. IEEE Transactions on Computer-Aided Design of Integrated Circuits. 2006.