Dworak J, Nepal K, Alves N, Shi Y, Imbriglia N, Bahar IR. Using Implications to Choose Tests Through Suspect Fault Identification. ACM Transactions on Design Automation of Electronic Systems (TODAES). 2013;18:14:1-14:19.
Nepal K, Ulusel O, Bahar IR, Reda S. Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. In: Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines. Washington, DC, USA: IEEE Computer Society; 2012. p. 65-8. (FCCM '12).
Jannaty P, Sabou FC, Le ST, Donato M, Bahar IR, Patterson W, et al. Shot-Noise-Induced Failure in Nanoscale Flip-Flops. IEEE Transactions on Electron Devices. 2012;59:800-6.
Ferri C, Papagiannopoulou D, Calimera A, Bahar IR. NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. Springer Journal of Electronic Testing: Theory and Applications (JETTA). 2012;28:349-63.
Alves N, Shi Y, Dworak J, Bahar IR, Nepal K. Enhancing online error detection through area-efficient multi-site implications. In: VLSI Test Symposium (VTS), 2011 IEEE 29th.; 2011. p. 241-6.
Ferri C, Marongiu A, Lipton B, Moreshet T, Bahar IR, Herlihy M, et al. {SoC-TM}: Integrated {HW/SW} support for transactional memory programming on embedded {MPSoCs}. In: Proceedings of the 7th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. New York, NY, USA: ACM; 2011. p. 39-48. (CODES+ISSS '11).