Li H, Mundy J, Patterson WR, Kazazis D, Zaslavsky A, Bahar IR. Prediction of soft errors in nanoscale CMOS circuits. In: Nanoelectronic Devices for Defense & Security (NANO-DDS) Conference. Arlington, VA; 2007.
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. In: Proceedings of the conference on Design, automation and test in Europe. San Jose, CA, USA: EDA Consortium; 2007. p. 576-81. (DATE '07).
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Techniques for {MRF} based implementation of multi-level combinational circuits. In: Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH 2006). Boston; 2006.
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Optimizing noise-immune nanoscale circuits using principles of Markov random fields. In: Proceedings of the 16th ACM Great Lakes symposium on VLSI. New York, NY, USA: ACM; 2006. p. 149-52. (GLSVLSI '06).
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Designing {MRF} based Error Correcting Circuits for Memory Elements. In: IEEE/ACM Design Automation and Test in Europe Conference. Munich, Germany; 2006. p. 1-2.
Nepal K, Bahar IR, Mundy J, Patterson WR, Zaslavsky A. Designing logic circuits for probabilistic computation in the presence of noise. In: Design Automation Conference, 2005. Proceedings. 42nd.; 2005. p. 485-90.