Publications

Found 369 results

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2009
Kadin, M., S. Reda, and A. Uht, "Central vs. distributed dynamic thermal management for multi-core processors: which one is better?", Proceedings of the 19th ACM Great Lakes symposium on VLSI, New York, NY, USA, ACM, pp. 137–140, 2009.
Reda, S., G. Smith, and L. Smith, "Maximizing the functional yield of wafer-to-wafer 3-D integration", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 17, no. 9: IEEE, pp. 1357–1362, 2009.
Do, H., and H. F. Silverman, "Stochastic particle filtering: A fast SRP-PHAT single source localization algorithm", Applications of Signal Processing to Audio and Acoustics, 2009. WASPAA '09. IEEE Workshop on, pp. 213-216, 2009.
Reda, S., "Using circuit structural analysis techniques for networks in systems biology", Proceedings of the 11th international workshop on System level interconnect prediction, New York, NY, USA, ACM, pp. 37–44, 2009.
2008
Levi, A., and H. F. Silverman, "A New Algorithm for the Estimation of Talker Azimuthal Orientation using a Large-Aperture Microphone Array", Submitted to IEEE International Conference on Multimedia and Expo (ICME), Hannover, Germany, June, 2008.
Gillette, M. D., and H. F. Silverman, "A Linear Closed-Form Algorithm for Source Localization from Time-Differences of Arrival", IEEE Signal Processing Letters, vol. 15, pp. 1-4, January, 2008.
Ferri, C., A. Viescas, T. Moreshet, I. R. Bahar, and M. Herlihy, "Energy Implications of Transactional Memory for Embedded Architectures", Workshop on exploiting parallelism with transactional memory and other hardwre assisted methods, April, 2008.
Ferri, C., S. Reda, and I. R. Bahar, "Parametric yield management for 3D ICs: Models and strategies for improvement", ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 4, no. 4: ACM, pp. 19, 2008.
Hargreaves, B., H. Hult, and S. Reda, "Within-die process variations: How accurately can they be statistically modeled?", Proceedings of the 2008 Asia and South Pacific Design Automation Conference: IEEE Computer Society Press, pp. 524–530, 2008.
Ferri, C., A. Viescas, T. Moreshet, I. R. Bahar, and M. Herlihy, "Energy efficient synchronization techniques for embedded architectures", Proceedings of the 18th ACM Great Lakes symposium on VLSI, New York, NY, USA, ACM, pp. 435–440, 2008.
Kadin, M., and S. Reda, "Frequency and voltage planning for multi-core processors under thermal constraints", Computer Design, 2008. ICCD 2008. IEEE International Conference on: IEEE, pp. 463–470, 2008.
Kadin, M., and S. Reda, "Frequency planning for multi-core processors under thermal constraints", Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on: IEEE, pp. 213–216, 2008.
2007
Do, H., and H. F. Silverman, "A Fast Microphone Array SRP-PHAT Source-Location Implementation using Coarse-to Fine Region Contraction(CFRC)", Proceedings of WASPAA2007, Mohonk(New Paltz), New York, pp. 295-298, October, 2007.
Nepal, K., I. R. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky, "Designing Nanoscale Logic Circuits Based on Markov Random Fields", J. Electron. Test., vol. 23, Norwell, MA, USA, Kluwer Academic Publishers, pp. 255–266, June, 2007.
Li, H., J. Mundy, W. R. Patterson, D. Kazazis, A. Zaslavsky, and I. R. Bahar, "Prediction of soft errors in nanoscale CMOS circuits", Nanoelectronic Devices for Defense & Security (NANO-DDS) Conference, Arlington, VA, June, 2007.
Tadesse, D., D. Sheffield, I. R. Bahar, and J. Grodstein, "Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models", ACM/IEEE Design Automation and Test in Europe Conference, Nice, France, April, 2007.
Ferri, C., S. Reda, and I. R. Bahar, "Strategies for improving the parametric yield and profits of 3D ICs", Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on: IEEE, pp. 220–226, 2007.
Kahng, A., S. Reda, and Q. Wang, "APlace: A High Quality, Large-Scale Analytical Placer", Modern Circuit Placement: Springer, pp. 167–192, 2007.
Meisner, D., and S. Reda, "Hardware libraries: An architecture for economic acceleration in soft multi-core environments", Computer Design, 2007. ICCD 2007. 25th International Conference on: IEEE, pp. 179–186, 2007.
Ferri, C., T. Moreshet, I. R. Bahar, L. Benini, and M. Herlihy, "A hardware/software framework for supporting transactional memory in a MPSoC environment", {ACM SIGARCH} Computer Architecture News, vol. 35, no. 1, pp. 47–54, 2007.
Nepal, K., I. R. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky, "Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits", Proceedings of the conference on Design, automation and test in Europe, San Jose, CA, USA, EDA Consortium, pp. 576–581, 2007.
Kahnq, A. B., S. Reda, and P. Sharma, "On-Line Adjustable Buffering for Runtime Power Reduction", Quality Electronic Design, 2007. ISQED'07. 8th International Symposium on: IEEE, pp. 550–555, 2007.