Publications

Found 368 results

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A
Adcock, J., Y. Gotoh, D. J. Mashao, and H. F. Silverman, "Microphone-Array Speech Recognition via Incremental MAP Training", Proceedings of ICASSP-1996, Atlanta, GA, pp. 897-900, May, 1996.
Adcock, J., J. DiBiase, M. Brandstein, and H. F. Silverman, "Practical Issues in the Use of a Frequency-Domain Delay Estimator for Microphone-Array Applications", Proceedings of Acoustical Society of America Meeting, Austin, Texas, pp. –, November, 1994.
Albera, G., and I. R. Bahar, "Power and Performance Tradeoffs using Various Cache Configurations", Power-Driven Microarchitecture Workshop, June, 1998.
Albera, G., and I. R. Bahar, "Power/Performance Advantages of a Victim Buffer in High-Performance Processors", IEEE Volta International Workshop on Low Power Design, March, 1999.
Alpert, C., A. Kahng, G. - J. Nam, S. Reda, and P. Villarrubia, "A semi-persistent clustering technique for VLSI circuit placement", Proceedings of the 2005 international symposium on Physical design: ACM, pp. 200–207, 2005.
Alvarado, V. M., and H. F. Silverman, Experimental Results Showing the Effects of Optimal Spacing between Elements of a Linear Microphone Array, , no. 68, Providence, RI 02912, LEMS, Division of Engineering, Brown University, April, 1990.
Alves, N., K. Nepal, J. Dworak, and I. R. Bahar, "Improving the testability and reliability of sequential circuits with invariant logic", Proceedings of the 20th symposium on Great lakes symposium on VLSI, New York, NY, USA, ACM, pp. 131–134, 2010.
Alves, N., A. Buben, K. Nepal, J. Dworak, and I. R. Bahar, "A Cost Effective Approach for Online Error Detection Using Invariant Relationships", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 5, pp. 788-801, May, 2010.
Alves, N., Y. Shi, J. Dworak, I. R. Bahar, and K. Nepal, "Enhancing online error detection through area-efficient multi-site implications", VLSI Test Symposium (VTS), 2011 IEEE 29th, pp. 241 -246, May, 2011.
Athanas, P. M., and H. F. Silverman, "An Adaptive Hardware Machine Architecture for Dynamic Processor reconfiguration", Proceedings of International Conference on Computer Design, Cambridge, MA, pp. 397-400, October, 1991.
Athanas, P. M., and H. F. Silverman, The Reconfigurable Communications Architecture of the Armstrong II, , no. 83, Providence, RI 02912, LEMS, Division of Engineering, Brown University, April, 1991.
Athanas, P. M., and H. F. Silverman, "Distributed Shared Memory in the UNIFY Programming Environment", Proceedings of ISMM Conference on Parallel and Distributed Computing, Washington, DC, pp. 433-437, October, 1991.
Athanas, P. M., and H. F. Silverman, "Armstrong II: A Loosely-Coupled Multiprocessor with a reconfigurable Communications Architecture", Proceedings of 1991 International Parallel Processing Symposium, Anaheim, CA, pp. 427-430, May, 1991.
Athanas, P. M., and H. F. Silverman, "PLADO: A Hardware Platform and Compiler for Adaptive Computing", 1992 Brown/MIT VLSI Conference, Providence, RI, 1992.
Athanas, P. M., and H. F. Silverman, Kernel Support for Distributed Global Memory on Loosely-Coupled Microprocessor Systems, , no. 71, Providence, RI 02912, LEMS, Division of Engineering, Brown University, June, 1990.
B
Bahar, I. R., H. Cho, G. Hachtel, E. Macii, and F. Somenzi, "Timing Analysis of Combinational Circuits using ADD's,", EDAC-94: IEEE European Conference on Design Automation, February, 1994.
Bahar, I. R., "Nanoscale Circuits and Architectures for Probabilistic Compuation in the Presence of Noise", Foundations of Nanoscience: Self-assembled Architectures and Devices, Snowbird, UT, April, 2006.
Bahar, I. R., D. Grunwald, and B. Calder, "A Comparison of Software Code Reordering and Victim Buffers", ACM SIGARCH Computer Architecture News, March, 1999.
Bahar, I. R., and S. Manne, "Power and Energy Reduction Via Pipeline Balancing", International Symposium on Computer Architecture, pp. 218-229, July, 2001.
Bahar, I. R., G. Albera, and S. Manne, "Power and Performance Tradeoffs using Various Caching Strategies", International Symposium on Low Power Electronics and Design, August, 1998.
Bahar, I. R., J. Mundy, and J. Chen, "A Probabilistic-Based Design Methodology for Nanoscale Computation", Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November, 2003.
Bahar, I. R., H. Y. Song, K. Nepal, and J. Grodstein, "Symbolic Failure Analysis of Complex CMOS Circuits Due to Excessive Leakage Current and Charge Sharing", IEEE Transactions on CAD of Integrated Circutis and Systems, vol. 24, no. 4, pp. 502-515, April, 2005.