Enhancing online error detection through area-efficient multi-site implications

TitleEnhancing online error detection through area-efficient multi-site implications
Publication TypeConference Paper
Year of Publication2011
AuthorsAlves, N., Y. Shi, J. Dworak, I. R. Bahar, and K. Nepal
Conference NameVLSI Test Symposium (VTS), 2011 IEEE 29th
Date PublishedMay
Keywordsarea-efficient multi site implications, checker logic, error detection, error-detecting hardware, fault coverage, fault location, input space, internal circuit sites, logic circuits, online error detection