Power Mapping and Modeling for ICs

Post-Silicon Power characterization Using Infrared emissions. Estimating power during design is difficult due to the possible wide range of workload stimulants to the processor. Designers have hard time validating and calibrating their power models. This project aims to overcome this difficulty by inverting the thermal emissions to spatial power estimates. Our method is non-intrusive and work during runtime leading to great benefits to processor designers. 

If you have recently purchased a computer, the large number of flavors available for the processor has probably bewildered you. Each one of these flavors gives a different price/performance trade-off. You probably wondered: why won't chip manufacturers make all their chips fast? Unfortunately, the answer is that they cannot! In recent years advanced nanometer fabrication technologies became prone to inherent statistical variations during fabrication. Thus, two chips that follow the same design and fabrication recipes could end up with completely different speeds after fabrication. In response to this problem, chip manufacturers test their chips after fabrication and sell the fastest ones for more money. At SCALE lab, we have been working on new techniques for accurate nanometer variability characterization and modeling techniques. We have implemented our own variability sensitive test structures and produced rigorous statistical techniques to model their measurements. We also work with our industry partners like IBM Corporation to analyze the variability data from their fabrication facilities.

Moore's law has been driving the pace of integrated semiconductor technology for the past four decades. While Moore's law was incorrectly predicted to demise numerous times in the past, it certainly faces insurmountable physical limits in the next decade. Even if these physical limits are mitigated, it is unlikely that such mitigation can be achieved through economically feasible means. To avoid these limitations, 3D integration has been advocated as a means to increase the scalability of semiconductor integration beyond lithographic shrinking. At SCALE lab, we work on solving some of the fundamental challenges of 3D technology. In particular yield we have devised new variability modeling techniques to model the unique variability sources in 3D integraiton. To address these variability sources, we developed 3D integration strategies to improve the parametric and functional yield of 3D integration.

Current People Involved:

- Sherief Reda
- Nowroz Adbullah
- Kapil Dev

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