Prediction of Soft Errors in Nanoscale Circuits and Design of Noise Tolerant Circuits

 

Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit operation characterized by lower supply voltages and smaller device sizes. Both of these downscaling approaches reduce the margin of immunity to thermal noise, alpha particle strikes, and threshold voltage variations. This project investigates the noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS flip-flops operated at both above and below threshold voltage levels.  In addition, we are exploring new approaches for noise-immune circuit design; some of these designs have been fabricated by MIT Lincoln Lab on a test chip.  This year focused on above threshold error rate analysis and exploring new logic styles to improve circuit noise immunity. This work is currently funded by DTRA.

Current People Involved:

- R. Iris Bahar
Pooya Jannaty
- Alex Zaslavsky
- Joseph Mundy
- William Patterson
- Marco Donato
- Kumud Nepal
- Profs. Schrimpf, Weller, Reed, Alles, and Bhuva (Vanderbilt Univeristy)