Laboratory and Homework Assignments

9/13/2017: Homework 1: switching activity analysis, due Wednesday, September 20, 2017 (hand in during class).

9/25/2017: Cadence software tutorials,

In preparation for homework #2, please complete the following Cadence tutorials by Thursday, September 28, 2017:

1. Logging on to the CCV machines and setting up Cadence Virtuoso
2. Creating an inverter with transistors using Cadence Virtuoso Schematic Capture
3. Running transient simulation on a circuit with Cadence Virtuoso

9/27/2017: Homework 2: MTCMOS circuits, due Wednesday, October 4, 2017.

Here is a link to the MTCMOS paper I referred to in class (you must be connected to the Brown network directly or via VPN):

S. Mutah, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847-853, August, 1995

10/25/2017: Homework 3: Approximate Circuits for Power-Efficient Computing, due Friday, November 3, 2017, by 5pm.

You will need to download the following file onto your home directory on the CCV maachines for this assignment.

• The tarred directory abacus_archive.tar (110MB compressed). NOTE: this was last updated 10/25/2017 at 4pm. If you have an older copy, please download this version instead.
• Login and use procedures for the CCV machines have slightly changed. Check the updated Setup file for more information.
• Once downloaded, you will need to "untar" the files to get the directory ABACUS_ENGN2912 (type "tar -xvf abacus_archive.tar"). Inside this directory are several other "subdirectories" that will be used for storing results generated by ABACUS. In addition, there are 2 scripts, launch_ABACUS.sh, and run_ABACUS_flow that you will be using for running your experiments.

• The ABACUS tool is described in the following research papers:

K. Nepal, Y. Li, R. I. Bahar, and S. Reda, "ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits,"; Design, Automation, and Test in Europe (DATE).March 2014.

K. Nepal, S. Hashemi, H. Tann, R. I. Bahar, S. Reda, "Automated High-Level Generation of Low-Power Approximate Computing Circuits,"; IEEE Transactions on Emerging Topics in Computing (TETCSI).Aug. 2016.

11/17/2017: Final Project Description

• Wednesday, November 22, 2017: Project selection
• Wednesday, November 29, 2017: Project proposal
• Wednesday, December 6, 2017: Progress report
• Monday, Wednesday, December 4, 6, 2017: Progress presentations
• Tuesday, December 19, 2017, 9am-noon: Final Project presenations
• Tuesday, December 19, 2017, 5pm: Final Report due

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