Handouts

 

Course Syllabus: online syllabus

Latest Draft of the lab manual: Laboratory Manual

Hints and Comments on Labs: Additional Lab Comments

User Manual for Agilent DSOX-2012A Oscilloscope: Scope User Manual

 

Verilog for a simple three-bit counter: First Class Example of a Verilog FSM

Rule for writing Verilog always blocks: Blocking and Non-blocking Assignments

Finite State Machine Example – Diabolical Coke™ Machine: FSM of a Coke Machine

Example of a Register Transfer Machine with program control,

aka – the stored program computer:  RTM System Example

CPLD Internal Structure: XC9500xl Data Sheet

Test Benches and What They Can Do (Lab 9): Primer from Lattice Semiconductor

 

Things to know about:

The fate of Moore’s Law – IEEE Spectrum article: The End of the Shrink

Shrinking may cost too much: Samsung's Little Expensive Step

What to do about power when it limits computing: Reversible Computing!

 

Lab Support Documents (these also appear in your lab manual):

Schematic diagram of the CPLD-II Board: CPLD-II Schematic

Handout on Setting Up DxDesigner: DxDesigner Setup Handout

Simulating the ENGN1630 CPLD-II Board: CPLD Simulation Handout

 

Full datasheets for your kit parts: FullDataSheets-ENGN1630.zip

 

Architectural Datasheet for the XC9500XL Family: XC9500XL Family

Datasheet for the XC9572XL: XC9572XL

 

Materials for FPGA labs:

Instructions for Download and Test: Instructions Labs B - C

Datasheet for the XC3S500E FPGA: XC3S500E

User Manual for the Spartan-3E FPGA evaluation board: Digilent Board

Schematic of supplementary I/O board for labs B, C, and D: I/O Board Schematic

Zip file of Xilinx project files for lab B – counter design: LabBwithCounters

Zip file of Xilinx project files for lab B – accumulator design: LabBwithAccumulators

Zip file of Xilinx project files for lab C: Zip File of Lab C

Test program for Lab C: Lab C Executable

Zip file of all material including Xilinx project files for lab D: Zip File of Lab D

 

Exam related materials from 2019:

Optional Practice Problem Set # 1: Problem Set 1

Optional Problem Set # 1: SOLUTIONS

Optional Practice Problem Set # 2: Problem Set 2

Optional Problem Set # 2: SOLUTIONS

Optional Practice Problem Set # 3: Problem Set 3 (for final)

Optional Problem Set # 3: SOLUTIONS

 

Exam related materials prepared by Prof. Patterson (from past years):

Material on Memory and FPGAs: PDFs on DRAM and FPGAs

Vocabulary of Logical System Design: Logic Terminology

Optional Homework Set # 1 for first exam: Optional Homework Set 1

Optional Homework Set # 1 answers: Answers_Set_1

Optional Homework Set #2 for final exam: Optional Homework Set 2

Optional Homework Set #2 answers: Answers Set 2

Formula Sheet from an intra-semester exam: Formula Sheet Mid-Semester

Formula Sheet from a final exam: Formula Sheet Final Exam

 

                      

 

 

 

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